As integrated circuits have become more complex employing more and more pins in a limited area, mutual inductance between pins has increased. In fact, a complex integrated circuit die is conventionally coupled to a significantly larger package to couple such integrated circuit die to a printed circuit board (“PCB”), as the pin density of such die may be too great to directly couple the die to the PCB.
Interconnect arrays are laid out in a pattern selected to reduce power/ground loop inductance by minimizing the “loop” between I/O pins and power or ground pins. One type of pattern used to avoid power/ground loops is known as a “checkerboard pattern” of pins. A checkerboard pattern of pins alternates power and ground pins to reduce mutual inductance; however, the checkerboard pattern leaves no pins for I/O signals.
Accordingly, it would be desirable and useful to provide a pinout with low loop inductance and increased signal pin density.